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functional block diagrams in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg451 in1 in2 in3 in4 in1 s1 d1 s2 d2 s3 d3 s4 d4 adg452 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 ADG453 switches shown for a logic "1" input rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos 5 v r on spst switches adg451/adg452/ADG453 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 features low on resistance (4 v ) on resistance flatness 0.2 v 44 v supply maximum ratings 6 15 v analog signal range fully specified @ 6 5 v, +12 v, 6 15 v ultralow power dissipation (18 m w) esd 2 kv continuous current 100 ma fast switching times t o n 70 ns t off 60 ns ttl/cmos compatible pin compatible upgrade for adg411/adg412/adg413 and adg431/adg432/adg433 applications relay replacement audio and video switching automatic test equipment precision data acquisition battery powered systems sample hold systems communication systems pbx, pabx systems avionics the ADG453 exhibits break-before-make switching action for use in multiplexer applications. inherent in the design is low charge injection for minimum transients when switching the digital inputs. product highlights 1. low r on (5 w max) 2. ultralow power dissipation 3. extended signal range the adg451, adg452 and ADG453 are fabricated on an enhanced lc 2 mos process giving an increased signal range that f ully extends to the su pply rails. 4. break-before-make switching this prevents channel shorting when the switches are configured as a multiplexer. (ADG453 only.) 5. single supply operation for applications where the analog signal is unipolar, the adg451, adg452 and ADG453 can be operated from a single rail power supply. the parts are fully specified with a single +12 v power supply and will remain functional with single supplies as low as +5.0 v. 6. dual supply operation for applications where the analog signal is bipolar, the adg451, adg452 and ADG453 can be operated from a dual power supply ranging from 4.5 v to 20 v. general description the adg451, adg452 and ADG453 are monolithic cmos devices comprising four independently selectable switches. they are designed on an enhanced lc 2 mos process that provides low power dissipation yet gives high switching speed and low on resistance. the on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion when switching audio signals. fast switching speed coupled with high signal bandwidth also make the parts suitable for video signal switching. cmos construction ensures ultralow power dissipa- tion making the parts ideally suited for portable and battery powered instruments. the adg451, adg452 and ADG453 contain four indepen- dent single-pole/single-throw (spst) switches. the adg451 and adg452 differ only in that the digital control logic is in- verted. the adg451 switches are turned on with a logic low on the appropriate control input, while a logic high is required for the adg452. the ADG453 has two switches with digital con- trol logic similar to that of the adg451 while the logic is in- verted on the other two switches. each switch conducts equally well in both directions when on and has an input signal range which extends to the supplies. in the off condition, signal levels up to the supplies are blocked.
adg451/adg452/ADG453Cspecifications 1 dual supply b version t min to parameter +25 8 ct max units test conditions/comments analog switch analog signal range v ss to v dd v on-resistance (r on ) 4.0 w typ v d = C10 v to +10 v, i s = C10 ma 57 w max on-resistance match between 0.1 w typ v d = 10 v, i s = C10 ma channels ( d r on ) 0.5 0.5 w max on-resistance flatness (r flat(on) ) 0.2 w typ v d = C5 v, 0 v, +5 v, i s = C10 ma 0.5 0.5 w max leakage currents 2 source off leakage i s (off) 0.02 na typ v d = 10 v, v s = 10 v; 0.5 2.5 na max test circuit 2 drain off leakage i d (off) 0.02 na typ v d = 10 v, v s = 10 v; 0.5 2.5 na max test circuit 2 channel on leakage i d , i s (on) 0.04 na typ v d = v s = 10 v; 1 5 na max test circuit 3 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 m a typ v in = v inl or v inh , all others = 2.4 v 0.5 m a max or 0.8 v respectively dynamic characteristics 3 t on 70 ns typ r l = 300 w , c l = 35 pf; 180 220 ns max v s = 10 v; test circuit 4 t off 60 ns typ r l = 300 w , c l = 35 pf; 140 180 ns max v s = 10 v; test circuit 4 break-before-make time delay, t d 15 ns typ r l = 300 w , c l = 35 pf; (ADG453 only) 5 5 ns min v s1 = v s2 = +10 v; test circuit 5 charge injection 20 pc typ v s = 0 v, r s = 0 w , c l = 1.0 nf; 30 pc max test circuit 6 off isolation 65 db typ r l = 50 w , c l = 5 pf, f = 1 mhz; test circuit 7 channel-to-channel crosstalk C90 db typ r l = 50 w , c l = 5 pf, f = 1 mhz; test circuit 8 c s (off) 15 pf typ f = 1 mhz c d (off) 15 pf typ f = 1 mhz c d , c s (on) 100 pf typ f = 1 mhz power requirements v dd = +16.5 v, v ss = C16.5 v digital inputs = 0 v or 5 v i dd 0.0001 m a typ 0.5 5 m a max i ss 0.0001 m a typ 0.5 5 m a max i l 0.0001 m a typ 0.5 5 m a max i gnd 3 0.0001 m a typ 0.5 5 m a max notes 1 temperature range is as follows: b version: C40 c to +85 c. 2 t max = +70 c . 3 guaranteed by design, not subject to production test. specifications subject to change without notice. rev. a C2C (v dd = +15 v, v ss = C15 v, v l = +5 v, gnd = 0 v. all specifications t min to t max unless otherwise noted.)
adg451/adg452/ADG453 rev. a C3C single supply b version t min to parameter +25 8 ct max units test conditions/comments analog switch analog signal range 0 v to v dd v on-resistance (r on )6 w typ v d = 0 v to 10 v, i s = C10 ma 810 w max on-resistance match between 0.1 w typ v d = 10 v, i s = C10 ma channels ( d r on ) 0.5 0.5 w max on-resistance flatness (r flat(on) ) 1.0 1.0 w typ v d = 0 v, +5 v, i s = C10 ma leakage currents 2, 3 source off leakage i s (off) 0.02 na typ v d = 0 v, 10 v, v s = 0 v, 10 v; 0.5 2.5 na max test circuit 2 drain off leakage i d (off) 0.02 na typ v d = 0 v, 10 v, v s = 0 v, 10 v; 0.5 2.5 na max test circuit 2 channel on leakage i d , i s (on) 0.04 na typ v d = v s = 0 v, 10 v; 1 5 na max test circuit 3 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 m a typ v in = v inl or v inh 0.5 m a max dynamic characteristics 4 t on 100 ns typ r l = 300 w , c l = 35 pf; 220 260 ns max v s = +8 v; test circuit 4 t off 80 ns typ r l = 300 w , c l = 35 pf; 160 200 ns max v s = +8 v; test circuit 4 break-before-make time delay, t d 15 ns typ r l = 300 w , c l = 35 pf; (ADG453 only) 10 10 ns min v s1 = v s2 = +8 v; test circuit 5 charge injection 10 pc typ v s = 0 v, r s = 0 w , c l = 1.0 nf; test circuit 6 channel-to-channel crosstalk C90 db typ r l = 50 w , c l = 5 pf, f = 1 mhz; test circuit 8 c s (off) 15 pf typ f = 1 mhz c d (off) 15 pf typ f = 1 mhz c d , c s (on) 100 pf typ f = 1 mhz power requirements v dd = +13.2 v digital inputs = 0 v or 5 v i dd 0.0001 m a typ 0.5 5 m a max i l 0.0001 m a typ 0.5 5 m a max v l = +5.5 v i gnd 4 0.0001 m a typ 0.5 5 m a max v l = +5.5 v notes 1 temperature range is as follows: b version: C40 c to +85 c. 2 t max = +70 c. 3 tested with dual supplies. 4 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = +12 v, v ss = 0 v, v l = +5 v, gnd = 0 v. all specifications t min to t max unless otherwise noted.)
adg451/adg452/ADG453Cspecifications 1 dual supply b version t min to parameter +25 8 ct max units test conditions/comments analog switch analog signal range v ss to v dd v on-resistance (r on )7 w typ v d = C3.5 v to +3.5 v, i s = C10 ma 12 15 w max on-resistance match between 0.3 w typ v d = 3.5 v, i s = C10 ma channels ( d r on ) 0.5 0.5 w max leakage currents 2, 3 source off leakage i s (off) 0.02 na typ v d = 4.5, v s = 4.5; 0.5 2.5 na max test circuit 2 drain off leakage i d (off) 0.02 na typ v d = 0 v, 5 v, v s = 0 v, 5 v; 0.5 2.5 na max test circuit 2 channel on leakage i d , i s (on) 0.04 na typ v d = v s = 0 v, 5 v; 1 5 na max test circuit 3 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 m a typ v in = v inl or v inh 0.5 m a max dynamic characteristics 4 t on 160 ns typ r l = 300 w , c l = 35 pf; 220 300 ns max v s = 3 v; test circuit 4 t off 60 ns typ r l = 300 w , c l = 35 pf; 140 180 ns max v s = 3 v; test circuit 4 break-before-make time delay, t d 50 ns typ r l = 300 w , c l = 35 pf; (ADG453 only) 5 5 ns min v s1 = v s2 = 3 v; test circuit 5 charge injection 10 pc typ v s = 0 v, r s = 0 w , c l = 1.0 nf; test circuit 6 off isolation 65 db typ r l = 50 w , c l = 5 pf, f = 1 mhz; test circuit 7 channel-to-channel crosstalk C76 db typ r l = 50 w , c l = 5 pf, f = 1 mhz; test circuit 8 c s (off) 15 pf typ f = 1 mhz c d (off) 15 pf typ f = 1 mhz c d , c s (on) 100 pf typ f = 1 mhz power requirements v dd = +5.5 v digital inputs = 0 v or 5 v i dd 0.0001 m a typ 0.5 5 m a max i ss 0.0001 m a typ 0.5 5 m a max i l 0.0001 m a typ 0.5 5 m a max v l = +5.5 v i gnd 4 0.0001 m a typ 0.5 5 m a max v l = +5.5 v notes 1 temperature range is as follows: b version: C40 c to +85 c. 2 t max = +70 c. 3 tested with dual supplies. 4 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = +5 v, v ss = C5 v, v l = +5 v, gnd = 0 v. all specifications t min to t max unless otherwise noted.) rev. a C4C
adg451/adg452/ADG453 rev. a C5C ordering guide temperature package model range options* adg451bn C40 c to +85 c n-16 adg451br C40 c to +85 c r-16a adg452bn C40 c to +85 c n-16 adg452br C40 c to +85 c r-16a ADG453bn C40 c to +85 c n-16 ADG453br C40 c to +85 c r-16a *n = plastic dip; r = small outline ic (soic). pin configuration (dip/soic) top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 in1 d1 s1 v ss gnd s4 d4 in4 in2 d2 s2 v dd v l s3 d3 in3 adg451 adg452 ADG453 absolute maximum ratings 1 (t a = +25 c unless otherwise noted) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +25 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to C25 v v l to gnd . . . . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v analog, digital inputs 2 . . . . . . . . . . . v ss C2 v to v dd +2 v or 30 ma, whichever occurs first continuous current, s or d . . . . . . . . . . . . . . . . . . . . 100 ma peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . . 300 ma (pulsed at 1 ms, 10% duty cycle max) operating temperature range industrial (b version) . . . . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c plastic package, power dissipation . . . . . . . . . . . . . . . 470 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 117 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . +260 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg451/adg452/ADG453 feature proprietary esd protection circuitry, permanent damage may occur on d evices subjected to high energy electrostatic discharges. therefore, proper esd precautions are reco mmended to avoid performance degradation or loss of functionality. truth table (ADG453) logic switch 1, 4 switch 2, 3 0 off on 1 on off soic package, power dissipation . . . . . . . . . . . . . . . . 600 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . 77 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kv notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at in, s or d will be clamped by internal diodes. current should be limited to the maximum ratings given. warning! esd sensitive device truth table (adg451/adg452) adg451 in adg452 in switch condition 01on 1 0 off
adg451/adg452/ADG453 rev. a C6C terminology v dd most positive power supply potential. v ss most negative power supply potential in dual supplies. in single supply applications, it may be connected to gnd. v l logic power supply (+5 v). gnd ground (0 v) reference. s source terminal. may be an input or output. d drain terminal. may be an input or output. in logic control input. r on ohmic resistance between d and s. d r on on resistance match between any two channels i.e., r on max C r on min. r flat(on) flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal range. i s (off) source leakage current with the switch off. i d (off) drain leakage current with the switch off. i d , i s (on) channel leakage current with the switch on. v d (v s ) analog voltage on terminals d, s. c s (off) off switch source capacitance. c d (off) off switch drain capacitance. c d , c s (on) on switch capacitance. t on delay between applying the digital control input and the output switching on. see test circuit 4. t off delay between applying the digital control input and the output switching off. t d off time or on time measured between the 90% points of both switches, when switching from one address state to another. see test circuit 5. crosstalk a measure of unwanted signal coupled through from one channel to another as a result of para- sitic capacitance. off isolation a measure of unwanted signal coupling through an off switch. charge a measure of the glitch impulse transferred injection from the digital input to the analog output dur- ing switching. 9 8 0 4 3 2 1 6 5 7 C16.5 v d or v s drain or source voltage C v t a = +25 8 c v l = +5v v dd = +5v v ss = C5v v dd = +13.5v v ss = C13.5v r on C v v dd = +16.5v v ss = C16.5v v dd = +15v v ss = C15v C13.5 C10.5 C7.5 C4.5 C1.5 1.5 4.5 7.5 10.5 13.5 16.5 figure 1. on resistance as a function of v d (v s ) for various dual supplies 15 C10 C5 0510 0 4 3 2 1 6 5 7 v d or v s drain or source voltage C v C15 r on C v +85 8 c v dd = +15v v ss = C15v v l = +5v +25 8 c C40 8 c figure 2. on resistance as a function of v d (v s ) for different temperatures with dual supplies
adg451/adg452/ADG453 rev. a C7C typical performance characteristicsC t a = +25 8 c v l = +5v 18 0 12 15 8 6 4 2 10 v d or v s drain or source voltage C v 3 6 0 12 14 16 v dd = +5v v ss = 0v 9 r on C v v dd = +13.5v v ss = 0v v dd = +15v v ss = 0v v dd = +16.5v v ss = 0v figure 3. on resistance as a function of v d (v s ) for various single supplies temperature C 8 c 10 25 leakage current C na 0.1 1.0 0.01 35 45 55 65 75 85 i s (off) i d (off) i d (on) v dd = +15v v ss = C15v v l = +5v v d = +15v v s = C15v figure 4. leakage currents as a function of temperature i l 1sw i + , i + 4sw v dd = +15v v ss = C15v v ss = +5v frequency C hz i supply C m a 10 100 1k 10k 100k 1m 10m 0.01 0.1 1.0 10 100 1k 10k 100k figure 5. supply current vs. input switching frequency v d or v s drain or source voltage C v 0 16 24 68 10 12 14 r on C v 12 11 10 9 8 7 6 5 4 3 2 1 0 C40 8 c +25 8 c +85 8 c v dd = +15v v ss = 0v v l = +5v figure 6. on resistance as a function of v d (v s ) for different temperatures with single supplies leakage current C na 0.5 C15 C12 0.4 0.3 0.2 C0.2 C0.3 C0.4 C0.5 0.1 0 C0.1 i d (on) v d or v s drain or source voltage C v i d (off) i s (off) C9 C6 C3 15 12 9 6 3 0 v dd = +15v v ss = C15v t a = +25 8 c v l = +5v figure 7. leakage currents as a function of v d (v s ) frequency C mhz 70 60 0 1 100 10 off isolation C db 50 40 30 20 10 v dd = +15v v ss = C15v v l = +5v figure 8. off isolation vs. frequency
adg451/adg452/ADG453 rev. a C8C fre q uency C hz 1k 120 100 10k 100k 1m 10m crosstalk C db v dd = 1 15v v ss = C15v v l = 1 5v r load = 50 v 100 20 0 40 60 80 100m figure 9. crosstalk vs. frequency 200 100 10 C3.5 1 C3.0 C2.5 C2.0 C1.5 C1.0 C0.5 0 loss C db frequency C mhz v dd = 1 15v v ss = C15v v l = 1 5v figure 10. frequency response with switch on application figure 11 illustrates a precise, fast, sample-and-hold circuit. an ad845 is used as the input buffer while the output operational amplifier is an ad711. during the track mode, sw1 is closed and the output v out follows the input signal v in . in the hold mode, sw1 is opened and the signal is held by the hold capacitor c h . adg451/ 452/453 ad845 ad711 +15v +5v sw2 s s d d sw1 +15v v in C15v C15v ch 2200pf C15v v out 75 v r c c c 1000pf +15v 2200pf figure 11. fast, accurate sample-and-hold circuit due to switch and capacitor leakage, the voltage on the hold capacitor will d ecrease with time. the adg451/ adg452/ADG453 minimizes this droop due to its low leakage specifications. the droop rate is further minimized by the use of a polystyrene hold capacitor. the droop rate for the circuit shown is typically 30 m v/ m s. a second switch, sw2, that operates in parallel with sw1, is included in this circuit to reduce pedestal error. since both switches will be at the same potential, they will have a differ- ential effect on the op amp ad711, which will minimize charge injec tion effects. pedestal error is also reduced by the compensation network r c and c c . this compensation net- work reduces the hold time glitch while optimizing the ac- quisition time. using the illustrated op amps and component values, the pedestal error has a maximum value of 5 mv over the 10 v input range. both the acquisition and settling times are 850 ns.
adg451/adg452/ADG453 rev. a C9C v s r on = v 1 /i ds v 1 i ds test circuit 1. on resistance test circuits i s (off) i s (off) v s v d test circuit 2. off leakage i d (on) v s v d test circuit 3. on leakage s d gnd +15v 0.1 m f C15v 0.1 m f +5v in v s 0.1 m f v ss v out c l 35pf v in v l v dd r l 300 v 50% adg451 3v adg452 v in v in v out 3v 50% 50% 50% 90% 90% t off t on test circuit 4. switching times gnd v ss ADG453 C15v v in in1, in2 v s1 v s2 s1 s2 v dd v l 0.1 m f +15v +5v 0.1 m f 0.1 m f d1 d2 v out1 v out2 c l2 35pf c l1 35pf r l1 300 v r l2 300 v 50% 90% v in v out1 v out2 50% 90% 90% 90% t d t d 3v 0v 0v 0v test circuit 5. break-before-make time delay
adg451/adg452/ADG453 rev. a C10C c l 10nf +15v +5v v l v gnd v dd C15v in v s r s s d v out v in = c l 3 d v out v in 3v v out d v out test circuit 6. charge injection C15v v in 0.1 m f v ss gnd in v s v dd v l r l 50 v v out +5v +15v 0.1 m f 0.1 m f sd test circuit 7. off isolation C15v 0.1 m f v ss gnd s d nc sd r l 50 v v out v s v in1 v in2 50 v 0.1 m f 0.1 m f +5v +15v channel-to-channel crosstalk = 20 3 log|v s /v out | test circuit 8. channel-to-channel crosstalk
adg451/adg452/ADG453 rev. a C11C 16-lead plastic dip (n-16) 16 18 9 0.840 (21.34) 0.745 (18.92) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.26) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 16-lead soic (r-16a) 16 9 8 1 0.3937 (10.00) 0.3859 (9.80) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 8 0 8 0.0196 (0.50) 0.0099 (0.25) x 45 8 outline dimensions dimensions shown in inches and (mm).
c3119aC0C2/98 printed in u.s.a. C12C

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